CGC=0, PCS=000, FRAC=0, PR=0, PCD=0, INUSE=0
PCC CLKCFG Register
| PCD | Peripheral Clock Divider Select 0 (0): Divide by 1 (pass-through, no clock divide). 1 (1): Divide by 2. 2 (2): Divide by 3. 3 (3): Divide by 4. 4 (4): Divide by 5. 5 (5): Divide by 6. 6 (6): Divide by 7. 7 (7): Divide by 8. |
| FRAC | Peripheral Clock Divider Fraction 0 (0): Fractional value is 0. 1 (1): Fractional value is 1. |
| PCS | Peripheral Clock Source Select 0 (000): Clock is off (or test clock is enabled) An external clock can be enabled for this peripheral. 1 (1): OSCCLK - System Oscillator Platform Clock(scg_sosc_plat_clk). 2 (2): SCGIRCLK - Slow IRC Clock(scg_sirc_plat_clk), (maximum is 8MHz). 3 (3): SCGFIRCLK - Fast IRC Clock(scg_firc_plat_clk), (maximum is 48MHz). 6 (6): SCGPCLK System PLL clock (scg_spll_plat_clk). |
| INUSE | Clock Gate Control 0 (0): Another core is not using this peripheral. 1 (1): Another core is using this peripheral. Software cannot modify the existing clocking configuration. |
| CGC | Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PR | Enable 0 (0): Peripheral is not present. 1 (1): Peripheral is present. |